1. Field of the Invention
The present invention relates to an analog-to-digital converter (ADC) calibrating method and an apparatus thereof, and more particularly, to a digitally calibrating method for a pipeline ADC and an apparatus thereof.
2. Description of the Prior Art
A pipeline analog-to-digital converter (ADC) is typical of an ADC for high speed and high resolution analog-to-digital conversion. Without the use of trimming or calibration techniques such as analogue calibration or digital calibration, the resolution of the pipeline ADC only approaches a degree of ten to twelve bits due to limitations such as capacitance mismatch induced during manufacturing, or a limited gain value of an operational amplifier. Additional circuitries or calibration techniques are required for implementing an ADC of higher resolution having more bits.
Please refer to U.S. Pat. No. 5,499,027 and U.S. Pat. No. 6,369,744, the contents of which are incorporated herein by reference. In the two patents mentioned above, pipeline ADCs including digitally self-calibrating functionality and related circuits thereof are disclosed. According to the above-mentioned patents, an ADC includes a pipeline structure. This pipeline structure includes a plurality of stages of analog-to-digital conversion units including an input stage, and a plurality of subsequent stages. Calibration of a specific stage of the analog-to-digital conversion units can eliminate errors caused by the limitations mentioned above. The ADC therefore also includes a calibration unit which corresponds to the specific stage of the analog-to-digital conversion units. The ADC utilizes conversion units of later stages out of the analog-to-digital conversion units, the calibration unit, and a set of calibration parameters corresponding to the specific stage of the analog-to-digital conversion units in order to calibrate the specific stage of the analog-to-digital conversion units.
In a calibration setup mode, the set of calibration parameters are derived by setting input signals of the specific stage of the analog-to-digital conversion units to be predetermined values, recording the output values of later stages, and performing proper calculations. Through this design, the set of calibration parameters are measured under the same conditions as that of a run mode, so as to precisely represent errors existed due to the circuits of the ADC.
The self-calibrating method mentioned above utilizes the conversion units of later stages out of the analog-to-digital conversion units in the pipeline structure in order to calibrate the specific stage of the analog-to-digital conversion units. It is therefore necessary that the precision of the conversion units of later stages approaches a certain degree in order to perform the calibration processes. To reach this goal, the circuits of the pipeline structure become much more power consuming or area-occupying (since better capacitor matching translates to larger capacitor area), or alternatively the circuits become much more complicated, or the error measurement or calibration are much more time-consuming.